Faster computer and electronic processors require smaller features for integrated circuits (IC), which in turn require smaller and smoother substrate surfaces. Chemical mechanical polishing (CMP) has become one of the most critical semiconductor fabrication technologies because it offers a superior means of removing unwanted topography in interlevel dielectric layers and achieving sufficient planarity for the creation of the IC or hybrid bonding for advanced packaging.
This application note describes the measurement and analysis advantages that white light interferometry (WLI) offers for the various CMP components. It also details an improvement study that investigated asperity behavior of the fluid layer under the wafer during the CMP process and revealed the effects of polishing and conditioning on the pads, as well as wafer polish results.
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